Wafer bumping technology can provide significant performance,form factor and cost advantages in a semiconductor package. Wafer bumping is anadvanced manufacturing process whereby metal solder balls or bumps are formedon the semiconductor wafer prior to dicing. Wafer bumps provide aninterconnection between the die and a substrate or printed circuit board in adevice. Solder bump composition and dimension depends on a number of factorssuch as form factor, cost and the electrical, mechanical and thermal performancerequirements of the semiconductor device.
JCET is experienced in a wide range of wafer bump alloys and processes,including printed bump, ball drop and plated technology with eutectic, leadfree and copper pillar alloys. Our wafer bumping offering includes wafer bumpand redistribution for 200mm and 300mm wafer sizes for full turnkey advancedflip chip and wafer level packaging solutions.
Flip Chip Packaging
Inflip chip packaging, the silicon die is directly attached to the substrateusing solder bumps instead of wire bonds, providing a dense interconnectionwith a much higher bandwidth, faster data rates and increased electrical andthermal performance. The solder bumps and/or copper pillar bumps are placed onthe active side of the device in a grid array pattern, either directly on I/Opads or routed from them. The most efficient implementation of flip chiptechnology occurs when the bump sits directly over the electronic cells towhich they are connected (bump on I/O). The flip chip process employs the useof capillary underfill material (CUF) or molded underfill material (MUF) in theopen spaces around the bumps and in the gap between the surface of the die andthe circuit board to produce a highly reliable and stable structure. Flip chipinterconnection is a key technology for a range of applications in theconsumer, networking, computing, mobile and automotive markets.
Wafer Level Packaging
Waferlevel packages (WLP) provide higher performance, functionality and speeds in asmall, thin, lightweight device. Wafer level packages are similar to flip chipin that they utilize advanced wafer bumps as the interconnection to circuitboards. Whereas flip chip interconnection typically uses smaller solder bumps,wafer level packages utilize larger solder bumps with no underfill. ManyWLPs employ repassivation as a stress buffer layer for the circuitry beneaththe bump. There are many variables to use in optimizing the design of a WLP,depending upon the cost-performance requirements. Wafer Level Packaging is asuccessful solution for established markets for mobile and handheld devices aswell as emerging markets such as the Internet of Things (IoT), wearable devicesand automotive electronics.
Re-Passivation and Redistribution Layer (RDL)
When additional die protection or additionalstructural support is required at the bump location, a single layer of polymerand metal is applied to the wafer. This process is referred to asre-passivation (RPV) since the addition of the polymer layer creates a secondlayer of passivation on the surface of the die. Repassivation is also used whenthe final metal bond pad is smaller than the diameter of the solder ball orunder bump metallurgy (UBM) structure. The additional layer of dielectricmaterial serves as a stress buffer layer, a planarizing medium and afinalpassivation layer to buffer the circuitry beneath the bump.In situations where a device may have to function in both a wire-bondableperipheral pad arrangement or as a Flip Chip or Wafer Level component, anadditional layer of lateral connections may be employed to reroute theinput/output (I/O) layout into a completely new footprint. Thisadditional layer is known as a Redistribution Layer or RDL and may befabricated from a thin layer of aluminum (Al), copper (Cu) or a combination ofaluminum and copper (AlCu). Re-passivation and RDL are key enablingtechnologies for advanced fan-out wafer level technology such as embedded Wafer Level Ball Grid Array(eWLB), fan-in Wafer Level Chip Scale Packaging (WLCSP), Integrated Passive Devices (IPD), and System-in-Package (SiP) solutions.